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A Novel High-speed Adder-Subtractor Design based on CNFET

by Shimaa I. Sayed, Salah El-Din H. Gamal
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International Journal of Applied Information Systems
Foundation of Computer Science (FCS), NY, USA
Volume 10 - Number 7
Year of Publication: 2016
Authors: Shimaa I. Sayed, Salah El-Din H. Gamal
10.5120/ijais2016451529

Shimaa I. Sayed, Salah El-Din H. Gamal . A Novel High-speed Adder-Subtractor Design based on CNFET. International Journal of Applied Information Systems. 10, 7 ( March 2016), 29-32. DOI=10.5120/ijais2016451529

@article{ 10.5120/ijais2016451529,
author = { Shimaa I. Sayed, Salah El-Din H. Gamal },
title = { A Novel High-speed Adder-Subtractor Design based on CNFET },
journal = { International Journal of Applied Information Systems },
issue_date = { March 2016 },
volume = { 10 },
number = { 7 },
month = { March },
year = { 2016 },
issn = { 2249-0868 },
pages = { 29-32 },
numpages = {9},
url = { https://www.ijais.org/archives/volume10/number7/878-2016451529/ },
doi = { 10.5120/ijais2016451529 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2023-07-05T19:02:51.666519+05:30
%A Shimaa I. Sayed
%A Salah El-Din H. Gamal
%T A Novel High-speed Adder-Subtractor Design based on CNFET
%J International Journal of Applied Information Systems
%@ 2249-0868
%V 10
%N 7
%P 29-32
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed design. In this paper, we present a novel high speed Adder-subtractor cell using CNFETs based on XOR gates and multiplexer. Presented design uses fourteen transistors, ten for full adder and four to modify the cell for subtraction. Simulation results show significant improvement in terms of delay and area saving with 48% and 11% respectively compared to the latest design. Simulations were carried out using HSPICE based on CNFET model with optimized design parameters.

References
  1. N. Weste, K. Eshragian, “Principles of CMOS VLSI Design: A Systems Perspective”, Addison-Wesley, 1993.
  2. R. Zimmermann, W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic”, Solid-State Circuits, IEEE Journal of. 32 (7) (1997) 1079–1090.
  3. K. Navi, M. Maeen, V. Foroutan, S. Timarchi, O. Kavehei, “A novel low power full-adder cell for low voltage”, Integration, the VLSI Journal, Elsevier 42 (4) (2009) 457–467.
  4. K. Navi, V. Foroutan, M. Rahimi Azghadi, M. Maeen, M. Ebrahimpour, M. Kaveh, O. Kavehei, “A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter”, Microelectronics Journal, Elsevier 40 (10) (2009) 1441–1448.
  5. K. Navi, M.H. Moaiyeri, R. Faghih Mirzaee, O. Hashemipour, B. Mazloom Nezhad, “Two new low-power full Adders based on majority-not gates”, Microelectronics Journal, Elsevier 40 (2009) 126–130.
  6. K. Navi, O. Kavehei, M. Rouholamini, A. Sahafi, S. Mehrabi, N. Dadkhahi, “Low power and high-performance 1 bit CMOS full-adder cell”, Journal of Computers. 3 (2) (2008) 48-54.
  7. M. H. Moaiyeri, A. Doostaregan and K. Navi, “Design of Energy-Efficient and Robust Ternary Circuits for Nanotechnology”, Circuits, Devices & Systems, Vol. 5, No. 4, 2011, pp. 285–296.
  8. K. Navi, M. H. Moaiyeri, R. Faghih Mirzaee, O. Hashemipour, and B. Mazloom Nezhad, “Two new lowpower full adders based on majority-not gates,” Elsevier, Microelectronics Journal, Vol. 40, No. 1, 2009, pp. 126-130.
  9. M. Alioto, G. Palumbo, “Analysis and comparison of the full adder block”, IEEE Trans. VLSI 10 (6), 2002, pp. 806–823.
  10. M. H. Moaiyeri, R. Faghih Mirzaee, and K. Navi, “Two new low-power and high-performance full adders”, Journal of Computers, Vol. 4, No. 2, 2009, pp. 119-126.
  11. A. Raychowdhury, K. Roy, “Carbon-nanotube-based voltage-mode multiple-valued logic design”, IEEE Transactions on Nanotechnology, 4 (2) (2005) 168–179.
  12. P. Keshavarzian, K. Navi, “Efficient Carbon Nanotube Galois Field Circuit Design”, IEICE, Electronics Express, 6 (9) (2009) 546-552.
  13. S. Lin, Y. B. Kim, F. Lombardi, “Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection”, IEEE transaction on nanotechnology, 9 (1) (2010) 30-37.
  14. S. Lin, Y. B. Kim, F. Lombardi, “CNTFET-Based Design of ternary logic Gates and Arithmetic Circuits”, IEEE Transaction on nanotechnology, 10 (2) (2011) 217-225.
  15. K. Navi, A. Momeni, F. Sharifi, P. Keshavarzian, “Two novel ultra-high speed carbon nanotube Full-Adder cells”, IEICE Electron. Express, 6 (19) (2009) 1395-1401.
  16. K. Navi, M. Rashtian, A. Khatir, P. Keshavarzian, O. Hashemipour, “High Speed Capacitor-Inverter Based Carbon Nanotube Full Adder”, Nanoscale Res. Lett., Springer, (2010) 859-862.
  17. S. A. Ebrahimi, P. Keshavarzian, “Ulta-Low Power and High Speed Full Adder Based-on CNTFET”, European journal of Scientific Research, 2012, Vol.80 No.3, pp.358-365.
Index Terms

Computer Science
Information Sciences

Keywords

Single walled CNT Adder-Subtractor High speed and Digital electronics.

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