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Design of 32-bit 3-Stage Pipelined Processor based on MIPS in Verilog HDL and Implementation on FPGA Virtex7
| International Journal of Applied Information Systems |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 10 - Number 9 |
| Year of Publication: 2016 |
| Authors: Husainali S. Bhimani, Hitesh N. Patel, Abhishek A. Davda |
10.5120/ijais2016451550
|
Husainali S. Bhimani, Hitesh N. Patel, Abhishek A. Davda . Design of 32-bit 3-Stage Pipelined Processor based on MIPS in Verilog HDL and Implementation on FPGA Virtex7. International Journal of Applied Information Systems. 10, 9 ( May 2016), 26-37. DOI=10.5120/ijais2016451550
Abstract
Reduced Instruction Set Compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor. This paper presents 32 bit 3 stage architecture inspired by MIPS. The Idea of this paper is to implement custom architecture like MIPS 32 bit architecture in VERILOG HDL. The last step is to implement MIPS on FPGA (Field programmable gate array). MIPS (Microprocessor without Interlocked pipeline stages) processors are one of the first successful classical RISC architecture.
References
- David A. Patterson, John L. Hennessy 2005. Computer organization and design, 3rd Edition, Elsevier.
- Sharda P. Katke, G.P. Jain,"Design and Implementation of 5 Stages Pipelined Architecture in 32 Bit RISC Processor", IJETAE, Volume 2. Issue 4. April 2012, pp. 340-346.
- Preetam Bhosle, Hari Krishna Moorthy, "FPGA Implementation of low power pipelined 32-bit RISC Processor", International Journal of Innovative Technology and Exploring Engineering (IJITEE), August 2012.
- Bai-ZhongYing, Computer Organization, Science Press, 2000.11.
- Charles E. Gimarc, Veljko M. Mhtinovic, "RISC Principles, Architecture, and Design", Computer Science Press Inc., 1989.
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