The week's pick
Reseach Article
Proficient Architecture for Vedic Multiplier using Various VLSI Design Techniques of Optimized Adder
| International Journal of Applied Information Systems |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 12 - Number 44 |
| Year of Publication: 2024 |
| Authors: V. Thamizharasan, Gokulapriya M., Madhubala M., Divya T., Ramya N. |
10.5120/ijca2023922620
|
V. Thamizharasan, Gokulapriya M., Madhubala M., Divya T., Ramya N. . Proficient Architecture for Vedic Multiplier using Various VLSI Design Techniques of Optimized Adder. International Journal of Applied Information Systems. 12, 44 ( Jul 2024), 34-40. DOI=10.5120/ijca2023922620
Abstract
Nowadays a mobile computing and multimedia applications are need for high-performance, reduced size and low-power. One of the most widely used operations in DSP is Multiplication. Different types of multipliers are available in digital. In these multipliers the Vedic multiplier is the most optimized multiplier used in signal processing module. In the existing method Vedic multiplier is designed with conventional adders, which having higher area utilization, lower speed, and power consumption. The proposed design presents a proficient Vedic multiplier architecture for high-performance applications. Vedic multiplier architecture is consisting of adders. The proposed scheme is to changing the architecture of multiplier by memory-oriented adder cell which specifically doing add the partial product of the multiplier in memory-based approach. Which is a high speed and low area adder. This Multiplier is functionally verified/simulated using Modelsim software and implemented to Spartan3E FPGA kit using Xilinx12.1 software. Also analyze the performance parameter like area, speed and power will be compared to conventional multiplier & adder architectures.
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