The week's pick
Reseach Article
An overview and Analysis of Low Power SRAM Design
| 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013) |
| Foundation of Computer Science USA |
| NCIPET - Number 1 |
| November 2013 |
| Authors: R. A. Burange, G. H. Agrawal |
| 8d776c7a-9b1e-4049-942a-380287f8eb08 |
R. A. Burange, G. H. Agrawal . An overview and Analysis of Low Power SRAM Design. 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013). NCIPET, 1 (November 2013), 0-0.
Abstract
Static Random Access memory (SRAM) is a matrix of static volatile memory cell. Different techniques used for power optimization and Challenges regarding reduction of static and dynamic powers are discussed. Power reduction of other supporting circuits like Sense amplifier is analyzed with respect to a standard design.
References
- Andrei Pavlov and Manoj Sachdev, "CMOS SRAM Circuit Design and Parametric Test in Nano-Scale Technologies", 2008 Springer Science Business Media B. V. ISBN 978-1-4020-8362-4 e-ISBN 978-1-4020-8363-1.
- Jawar Singh, Jimson Mathew, Saraju P. Mohanthy and Dhiraj K. Pradhan, "Single Ended Static Random Memory for Low-Vdd, High-Speed Embedded Systems",22nd International Conference on VLSI Design 2009.
- Bharadwaj S. Amrutur and Mark A. Horowitz, "Speed and Power Scaling of SRAM's", IEEE Transactions on Solid-State Circuits, vol. 35,pp. 175-185, no. 2, February 2000.
- Sreerama Reddy G M and P Chandrasekhara Reddy, "Design and Implementation of 8K-bits Low Power SRAM in 180nm Technology", Proceedings of the International Multi Conference of Engineers and Compute Scientists 2009 Vol. II IMECS 2009, March -20, 2009, Hong Kong.
- Byung-Do Yang, "A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations", IEEE journal of solid-state circuits, vol. 45, no. 10, October 2010.
- Keejong Kim, Hamid Mahmoodi, Member, IEEE, and Kaushik Roy, Fellow, IEEE. ,"A Low-Power SRAM Using Bit-Line Charge-Recycling", IEEE journal of solid-state circuits, vol. 43, no. 2, February 2008.
- Anh-Tuan Do, Zhi-Hui Kong, Kiat-Seng Yeo, and Jeremy Yung Shern Low, " Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM". IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 19, no. 2, February 2011
- Ramy E. Aly and Magdy A. Bayoumi, Fellow, IEEE,"Low-Power Cache Design Using 7T SRAM Cell", IEEE Transactions on circuits and systems—II: express briefs, vol. 54, no. 4, April 2007.
- Kavita Khare, Nilay Khare, Vijendra Kumar Kulhade, Pallavi Deshpande, "VLSI Design And Analysis Of Low Power 6T SRAM Cell Using Cadence Tool", IESE 2008 Proc. 2008, lohor Bahru, Malaysia.
- "A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations" by Byung-Do Yang, IEEE Journal of solid-state circuits, vol. 45, No. 10,pp. 2173 - 2183, October 2010.
- "Design of a High Performance and Low Power 1Kb 6T SRAM using Bank Partitioning Method" by Kumkum Verma, Sanjay Kumar Jaiswal and Mohammad Ayoub Khan, 2011 International Conference on Multimedia, Signal Processing and Communication Technologies, pp. 56 -59.
- "A Low-Power Embedded SRAM for Wireless Applications" by Stefan Cosemans, Student Member, IEEE, Wim Dehaene, Senior Member, IEEE, and Francky Catthoor, Fellow, IEEE, Journal of solid-state circuits, vol. 42, No. 7, pp. 1607 -1617 , July 2007
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